1. Field of the Invention
This invention relates to a semiconductor memory device and more particularly to an improvement of a redundancy structure in a nonvolatile memory device for fixed data.
2. Description of the Related Art
Nonvolatile memory devices include, for example, those having memory cells which are previously and selectively doped with an impurity under gate electrodes and adapted to store information of 1 or 0 corresponding to high or low threshold voltage. These memory devices have been widely put into practical use for various systems such as microprocessor-applied components and the like since desired data can simply be written in the devices by using a mask which results in a relatively cheaper cost for mass production. The memory devices are, therefore, suitable for and largely used as memory means for storing information for characters and symbols in various word-information processing systems such as a word processor and the like. Those nonvolatile memory devices for fixed data are inevitably required to have a larger storage capacity, but their defective bit lines are rather hard to be repaired by providing a redundancy circuit as in a DRAM and SRAM. As a result, ensuring a high yield becomes difficult in the production of the devices, under the trend of the capacity increasing from 8M and 16M bits as conventionally to the future 32M, 64M and more bits.
Next, the redundancy circuit will be detailed. Redundancy recovery techniques are is generally known to be effective in DRAM and SRAM for prevention of lowering yield of the larger storage devices. FIG. 1 exemplifies a redundancy circuit for a memory device (S. Konishi et al. IEEE ISSCC 1982, Digest of Technical Papers, pp. 258-259), wherein the memory device is provided with two redundant lines (spare lines) S1 and S2. When a defective cell C1 is present on a normal memory cell array 11, a spare decoder 13 is programmed to select an address signal corresponding to that line. FIG. 2 details the spare decoder comprising two decoders D11 and D12) which provides the relief by redundancy of two defective points.
Programming (write-in) of the spare decoder on the redundancy circuit has conventionally been carried out by means of fuse lines. The fuse lines are usually built up with polysilicon wire and the like. Upon programming, a laser beam or a high voltage is applied to the predetermined fuse in a fuse line. For example, fuses on a fuse line F1 or F2 in FIG. 2 are selectively broken down (e.g. by the application of a laser beam or electrically) to define the address of memory cell line containing a defective bit. Thereafter, either spare decoder D11 or D12 is selected and at the same time a selection inhibiting signal for the cell line to be repaired is transmitted to a cell line decoder 14. As a result, a spare line S1 or S2 is selected in place of a normal cell line to complete the relief operation by redundancy.
To apply the above redundancy structure of a RAM to a nonvolatile memory device for fixed data, written data must be repaired by redundancy as well as by a memory cell line. Thus, not only a peripheral circuit such as the spare decoder and the like but also spare memory cells are to be programmed in a nonvolatile memory device. The programming is possible in principle by using an electrical fuse or an electrically writing-enable non-volatile memory. Using the fuse or the non-volatile memory for programming allows a retest to immediately be conducted after a die sort test which is simultaneously effected at fuse-blowing or electrically writing-in.
However, these techniques have been rarely practiced due to such problems that the programming unfavorably requires a high voltage 2 to 3 times higher than normally supplied voltage with a larger current, leading to a higher breakdown voltage requirement and an additional chip area. Also, a laser fusing technique using a number of fuses in rows is difficult to be applied for a nonvolatile memory device due to the limited cell area of the device.